1. Field of the Invention
This invention relates to information technology (IT), and more particularly, to an optimized peripheral device configuration data sequential handling method and system which is designed for use with a computer platform equipped with a peripheral interface controller that is connectable with multiple peripheral devices, such as a PCI (Peripheral Component Interconnect) controller, for providing the PCI peripheral interface controller with an optimized configuration data sequential handling function that can sequentially handle the original configuration data stored in a built-in OPROM (Option ROM, where ROM=Read-Only Memory) in each of the connected peripheral devices by means of a shadow RAM (Random-Access Memory) having a limited capacity in an optimized manner.
2. Description of Related Art
PCI (Peripheral Component Interconnect) is a standard peripheral bus architecture that is widely utilized on computer platforms, such as desktop computers, notebook computers, and network servers. The PCI interface is used connecting the CPU (Central Processing Unit) of the computer platform externally to circuit cards that can be used for connections to various kinds of peripheral devices, such as monitor adapters, hard disk drives, CD-DVD drivers, network adapters, to name just a few, for the purpose of allowing the CPU to exchange data with these peripheral devices.
PCI peripheral devices are typically equipped with an OPROM (Option ROM, where ROM=Read-Only Memory) module for storing a set of configuration data about the associated peripheral device. When a PCI peripheral device is connected to a computer platform, the PCI peripheral interface controller can retrieve the OPROM-embedded configuration data from each connected peripheral device for initialization purpose. Fundamentally, RAM (Random-Access Memory) has a faster access speed than ROM (Read-Only Memory). Therefore, in order to speed up the initialization process, a special memory area, customarily referred to as “shadow RAM”, is predefined in the RAM of the computer platform, such that during initialization process, the OPROM-embedded original configuration data can be copied to the shadow RAM for increased performance during the initialization process.
During actual operation, the computer platform will assign a storage area in the shadow RAM for each of the currently-connected peripheral devices, and then duplicate a shadow copy of the OPROM-embedded original configuration data to the assigned storage area in the shadow RAM for processing during initialization. For example, if there are 5 peripheral devices PCI(1), PCI(2), PCI(3), PCI(4), and PCI(5) which are installed to a PCI peripheral interface controller having 5 PCI buses PCI_BUS(1), PCI_BUS(2), PCI_BUS(3), PCI_BUS(4), and PCI_BUS(5) in such a manner that PCI(1) is installed to PCI_BUS(3); PCI(2) is installed to PCI_BUS(5); PCI(3) is installed to PCI_BUS(4); and PCI(5) is installed to PCI_BUS(2). Then, in this case, since the computer platform typically scans these 5 PCI buses in the sequence of PCI_BUS(1)→PCI_BUS(2)→PCI_BUS(3)→PCI_BUS(4)→PCI_BUS(5), the installed 5 PCI peripheral devices will be handled in the sequence of PCI(4)→PCI(5)→PCI(1)→PCI(3)→PCI(2). In this case, the computer platform will define 5 storage areas in the shadow RAM and handle the configuration of these 5 PCI peripheral devices in the sequence of PCI(4)→PCI(5)→PCI(1)→PCI(3)→PCI(2).
In practice, most computer platforms have a shadow RAM capacity of only 128 KB (kilobyte), within the address range of C0000h-DFFFFh. Therefore, the shadow RAM can only support a limited number of peripheral devices at the same time. For example, if a must-have peripheral device, such as a VGA adapter, has an OPROM-embedded original configuration data amount of 32 KB, then during initialization of the VGA adapter, its configuration data will take up 32 KB of memory space in the shadow RAM, and whereupon the remaining memory space of the shadow RAM will be 128−32=96 KB. Under this condition, the performance of the initialization of the other PCI peripheral devices will depend on their handling sequence. For example, if 4 PCI peripheral devices PCI(1), PCI(2), PCI(3), PCI(4) respectively have an OPROM-embedded original configuration data amount of 64 KB, 64 KB, 32 KB, and 24 KB, and whose runtime data amounts are respectively reduced to 6 KB, 32 KB, 32 KB, and 16 KB, then in this case, as shown in the following table, if the handling sequence for these 4 PCI peripheral device is PCI(1)→PCI(2)→PCI(3)→PCI(4), then all of these 4 PCI peripheral devices can be handled.
PeripheralOriginalRuntimedevice HandlingConfigurationDataRemaining SpaceSequenceData AmountAmountof Shadow RAMPriority 1: PCI(1)64 KB 6 KB96 − 6 = 90 KB(>64 KB)Priority 2: PCI(2)64 KB32 KB90 − 32 = 58 KB(>32 KB)Priority 3: PCI(3)32 KB32 KB58 − 32 = 26 KB(>24 KB)Priority 4: PCI(4)24 KB16 KB26 − 16 = 10 KBOn the other hand, as shown in the following table, if the handling sequence for these 4 PCI peripheral device is PCI(2)→PCI(3)→PCI(4)→PCI(1), then only the first three of these 4 PCI peripheral devices can be handled.
PeripheralOriginalRuntimedevice HandlingConfigurationDataRemaining SpaceSequenceData AmountAmountof Shadow RAMPriority 1: PCI(2)64 KB32 KB96 − 32 = 64 KB(>32 KB)Priority 2: PCI(3)32 KB32 KB64 − 32 = 32 KB(>24 KB)Priority 3: PCI(4)24 KB16 KB32 − 16 = 16 KB(<64 KB)Priority 4: PCI(1)64 KBXX
From the above table, it can be seen that when the third-priority peripheral device PCI(4) is being handled, the remaining space of the shadow RAM is only 16 KB, which is insufficient to accommodate the 64 KB data amount of the fourth-priority peripheral device PCI(1); and therefore, the last peripheral device PCI(1) cannot be handled.